台积电:3nm 工艺相比 5nm 密度提升 1.7 倍,功耗降低 25-30%

12 月 25 日消息,根据芯智讯报道,中国集成电路设计业 2021 年会暨无锡集成电路产业创新发展高峰论坛于 12 月 22 日举办。台积电(南京)有限公司总经理罗镇球做了主题为《半导体产业的新时代》的主题演讲。According to the news on December 25, according to Xinzhixun, China’s IC Design Industry 2021 Conference and Wuxi IC Industry Innovation and Development Summit Forum will be held on December 22. Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., gave a keynote speech on “The New Era of Semiconductor Industry”.
Luo Zhenqiu announced that although many people say that Moore’s Law is slowing down or gradually disappearing, in fact, TSMC is using new technology to prove that Moore’s Law is still advancing. TSMC’s 7nm process was launched in 2018, 5nm was launched in 2020, and the 3nm process will be launched as scheduled in 2022, and the 2nm process is also being developed smoothly.
According to the roadmap shown by TSMC, from the 5nm process to 3nm, the transistor logic density can be increased by 1.7 times, the performance can be increased by 11%, and the power consumption can be reduced by 25%-30% under the same performance.
How to achieve further reduction of transistors in the future, Luo Zhenqiu revealed two directions: 1. Change the structure of transistors: Samsung will use a new “Gate Surround Transistor” (GAA) structure in the 3nm process, while TSMC 3nm will still use fins. Type field effect transistor (FinFET) structure. However, TSMC has developed the Nanosheet/Nanowire transistor structure (similar to GAA) for more than 15 years and has achieved very solid performance.
2. Changing the material of the transistor: Two-dimensional materials can be used to make the transistor. This will make the power consumption control better, and the performance will be stronger.
IT Home has learned that Luo Zhenqiu also said that in the future, 3D packaging technology will be used to improve chip performance and reduce costs. At present, TSMC has integrated advanced packaging related technologies into a “3DFabric” platform.
In addition, TSMC will also apply the 5nm process platform “N5A” in ADAS and smart digital cockpit automotive chips. It is expected to be launched in the third quarter of 2022, which can meet automotive process standards such as AEC-Q100, ISO26262, and IATF16949.

罗镇球宣布,虽然有很多人说摩尔定律在减速或者在逐渐消失,可事实上台积电正在用新工艺证明了摩尔定律仍在持续往前推进。台积电的 7nm 工艺是在 2018 年推出的,5nm 在 2020 年推出,在 2022 年会如期推出 3nm 工艺,而且 2nm 工艺也在顺利研发。

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根据台积电展示的路线图,从 5nm 工艺至 3nm,晶体管逻辑密度可以提升 1.7 倍,性能提升 11%,同等性能下功耗可以降低 25%-30%。

如何在未来实现晶体管的进一步微缩,罗镇球透露了两个方向:

1、改变晶体管的结构:三星将在 3nm 制程采用全新的“环绕栅极晶体管”(GAA)结构,而台积电 3nm 依旧采用鳍式场效晶体管(FinFET)结构。不过,台积电研发 Nanosheet / Nanowire 的晶体管结构(类似 GAA)超过 15 年,已经达到非常扎实的性能。

2、改变晶体管的材料:可以使用二维材料做晶体管。这会使得功耗控制得更好,而且性能会更强。

IT之家了解到,罗镇球还表示未来将运用 3D 封装技术来提高芯片的性能,降低成本。目前,台积电已经将先进封装相关技术整合为“3DFabric”平台。

除此之外,台积电还将在 ADAS 和智能数字驾驶舱的汽车芯片应用 5nm 工艺平台“N5A”,预计将在 2022 年第三季度推出,能够符合 AEC-Q100、ISO26262、IATF16949 等汽车工艺标准。

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